1. Field of the Invention
The invention relates generally to methods for fabricating hybrid orientation substrates. More particularly, the invention relates to methods for fabricating hybrid orientation substrates with enhanced performance.
2. Description of the Related Art
Recent advances in semiconductor manufacturing technology have involved the use of hybrid orientation substrates. Hybrid orientation substrates are semiconductor substrates that include multiple surface semiconductor layers having differing crystallographic orientations. Typically, semiconductor devices of differing polarity or differing conductivity type are formed and located within the multiple surface semiconductor layers having the differing crystallographic orientations. Generally, the semiconductor devices of differing polarity or differing conductivity type benefit from the differing crystallographic orientations in terms of enhanced performance, such as enhanced charge carrier mobility. Thus, with respect to individual semiconductor devices a particular polarity or conductivity type thereof is mated with a particular crystallographic orientation to provide the semiconductor devices with enhanced performance.
As a specific example in accordance with the foregoing device polarity and surface semiconductor layer crystallographic orientation mating, n-FETs are preferably fabricated within (100) silicon or silicon-germanium alloy surface semiconductor layers. Analogously, p-FETs are preferably fabricated within (110) silicon or silicon-germanium alloy surface semiconductor layers.
While hybrid orientation substrates are thus desirable within the semiconductor fabrication art, hybrid orientation substrates are nonetheless not entirely without problems. In particular, hybrid orientation technology substrates are often formed using epitaxial methods for forming at least one of the different crystallographic orientation layers that comprise a hybrid orientation technology substrate. Since such epitaxial layers are often formed bounded by dielectric masking and blocking layers, such epitaxial layers are often formed only with defects.
Various semiconductor structures having desirable properties, and methods for fabrication thereof, are disclosed within the semiconductor fabrication art.
For example, Yang et al., in “High Performance CMOS Fabricated on Hybrid Substrate With Different Crystallographic Orientations,” IEEE International Electron Devices Meeting Technical Digest, 8-10 Dec. 2003, pages 18.7.1-18.7.4, teaches one particular method for fabricating a hybrid orientation substrate that may be used for fabricating a complementary metal oxide semiconductor (CMOS) structure. The particular method uses a semiconductor substrate laminating and bonding method followed by a selective epitaxial growth method.
A need for enhanced performance of both n-FET devices and p-FET devices within CMOS structures is likely to continue to be of importance within CMOS device fabrication. To that end, the use of hybrid orientation substrates for fabrication of CMOS devices is also likely to continue. Thus, a need to fabricate hybrid orientation substrates with enhanced performance and enhanced manufacturability is similarly also likely to continue.